---
title: References
url: 'https://timeloop.csail.mit.edu/references'
markdown: 'https://timeloop.csail.mit.edu/references.md'
date: '2024-08-15'
description: 'Tutorial Websites Timeloop/Accelergy tutorial SparseLoop tutorial Background Material V. Sze, Y.-H. Chen, T.-J. Yang, J. S. Emer, Efficient Processing of Deep Neural Networks, Synthesis Lectures on Computer Architecture, Morgan & Claypool Publishers, 2020. [book] [flyer] T. Krishna; H. Kwon;…'
taxonomy:
  category:
    - docs
---

[](#)  [ Overview ](https://timeloop.csail.mit.edu/)      References    

# References

## Tutorial Websites

- [Timeloop/Accelergy tutorial](http://accelergy.mit.edu/tutorial.html)
- [SparseLoop tutorial](https://accelergy.mit.edu/sparse_tutorial.html)

## Background Material

V. Sze, Y.-H. Chen, T.-J. Yang, J. S. Emer, Efficient Processing of Deep Neural Networks, Synthesis Lectures on Computer Architecture, Morgan & Claypool Publishers, 2020. [\[book\]](http://www.morganclaypoolpublishers.com/catalog_Orig/product_info.php?cPath=22&products_id=1530) [\[flyer\]](https://accelergy.mit.edu/book_flyer.pdf)

T. Krishna; H. Kwon; A. Parashar; M. Pellauer; A., Data Orchestration in Deep Learning Accelerators , Morgan & Claypool, 2020. [\[DOI\]](https://doi.org/10.2200/S01015ED1V01Y202005CAC052)

## Tool Related Papers

A. Parashar, P. Raina, Y. S. Shao, Y. Chen, V. A. Ying, A. Mukkara, R. Venkatesan, B. Khailany, S. W. Keckler, and J. Emer, "Timeloop: A systematic approach to DNN accelerator evaluation," IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS), 2019. [\[paper\]](https://people.csail.mit.edu/emer/papers/2019.03.ispass.timeloop.pdf)

Y. N. Wu, P.-A. Tsai, A. Parashar, V. Sze, J. S. Emer, "Sparseloop: An Analytical Approach To Sparse Tensor Accelerator Modeling", arXiv, May 2022. [\[paper\]](https://arxiv.org/abs/2205.05826)

Y. N. Wu, P.-A. Tsai, A. Parashar, V. Sze, J. S. Emer, “Sparseloop: An Analytical, Energy-Focused Design Space Exploration Methodology for Sparse Tensor Accelerators,” IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS), March 2021 [\[paper\]](http://accelergy.mit.edu/ispass2021/sparseloop_abstract.pdf)

Y. N. Wu, J. S. Emer, V. Sze, “Accelergy: An Architecture-Level Energy Estimation Methodology for Accelerator Designs,” International Conference on Computer Aided Design (ICCAD), November 2019 [\[paper\]](https://people.csail.mit.edu/emer/papers/2019.11.iccad.accelergy.pdf) [\[slides\]](http://accelergy.mit.edu/slides.pdf)

## Reference Design Papers

Y.H. Chen, T. Krishna, J. Emer, V. Sze, "Eyeriss: An Energy-Efficient Reconfigurable Accelerator for Deep Convolutional Neural Networks", IEEE Journal of Solid State Circuits (JSSC), ISSCC Special Issue, Vol. 52, No. 1, pp. 127-138, January 2017. [\[paper\]](https://people.csail.mit.edu/emer/papers/2017.01.jssc.eyeriss_design.pdf)

Y.S. Shao, J. Clemons, R. Venkatesan, B. Zimmer, M. Fojik, N. Jiang, B. Keller, A. Klinefelter, N. Pinckney, P. Raina, S. Tell, Y. Zhang, W.J. Dally, J. Emer, C.T. Gray, B. Khailany, S.W. Kecker, "Simba: Scaling Deep-Learning Inference with Multi-Chip-Module-Based Architecture", 52nd Annual IEEE/ACM International Symposium on Microarchitecture (MICRO), October 2019. [\[paper\]](https://people.eecs.berkeley.edu/~ysshao/assets/papers/shao2019-micro.pdf)

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---

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