---
title: Design
url: 'https://timeloop.csail.mit.edu/v4/input-formats/design'
markdown: 'https://timeloop.csail.mit.edu/v4/input-formats/design.md'
date: '2024-08-15'
description: 'The complete accelerator design is specified to Timeloop with three top-level keys in the YAML input (two of which are optional): Architecture - The basic topology of the architecture Components - Compound components that may be instantiated in the architecture Constraints (optional) - Constraints…'
taxonomy:
  category:
    - docs
---

[](#)  [ Overview ](https://timeloop.csail.mit.edu/)     [ Timeloop+Accelergy v4 ](https://timeloop.csail.mit.edu/v4)     [ Input Formats ](https://timeloop.csail.mit.edu/v4/input-formats)      Design    

# Design

The complete accelerator design is specified to Timeloop with three top-level keys in the YAML input (two of which are optional):

- [Architecture](https://timeloop.csail.mit.edu/v4/input-formats/design/./architecture) - The basic topology of the architecture
- [Components](https://timeloop.csail.mit.edu/v4/input-formats/design/./components) - Compound components that may be instantiated in the architecture
- [Constraints](https://timeloop.csail.mit.edu/v4/input-formats/design/./constraints) (optional) - Constraints on legal mappings to the archecture, e.g., limits on loop reorders or bypassing
- [Sparse Optimizations](https://timeloop.csail.mit.edu/v4/input-formats/design/./sparse-optimizations) (optional) - Specification of **sparse acceleration features** or SAFs incorporated in to the design

Therefore a skeleton of a complete design specification will look like:

```YAML
architecture:
      ....

constraints: # Extra constraints that are not embedded in the architecture
     ....

sparse_optimizations: # Extra sparse optimizations that are not embedded in the architecture
     ...

components: # Compound components that may be instantiated in the architecture
     ...
```

[accessibility](https://accessibility.mit.edu/)

 [ ](https://timeloop.csail.mit.edu/v4/input-formats/problem) [](https://timeloop.csail.mit.edu/v4/input-formats/design/architecture)

---

## Navigation

- Parent: [Input Formats](https://timeloop.csail.mit.edu/v4/input-formats.md)
- Previous: [Problem](https://timeloop.csail.mit.edu/v4/input-formats/problem.md)
- Next: [Mapper](https://timeloop.csail.mit.edu/v4/input-formats/mapper.md)
- Children:
  - [Architecture](https://timeloop.csail.mit.edu/v4/input-formats/design/architecture.md)
  - [Sparse Optimizations](https://timeloop.csail.mit.edu/v4/input-formats/design/sparse-optimizations.md)
  - [Constraints](https://timeloop.csail.mit.edu/v4/input-formats/design/constraints.md)
  - [Components](https://timeloop.csail.mit.edu/v4/input-formats/design/components.md)