Design

The complete accelerator design is specified to Timeloop with three top-level keys in the YAML input (two of which are optional):

• Architecture - The basic topology of the architecture
• Sparse Optimizations (optional) - Specification of sparse acceleration features or SAFs incorporated in to the design
• Constraints (optional) - Constraints on legal mappings to the archecture, e.g., limits on loop reorders or bypassing

Therefore a skeleton of a complete design specification will look like:

architecture:
      ....

constraints: 
     ....

sparse-optimizations:
     ...

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