V. Sze, Y.-H. Chen, T.-J. Yang, J. S. Emer, Efficient Processing of Deep Neural Networks, Synthesis Lectures on Computer Architecture, Morgan & Claypool Publishers, 2020. [book] [flyer]
T. Krishna; H. Kwon; A. Parashar; M. Pellauer; A., Data Orchestration in Deep Learning Accelerators , Morgan & Claypool, 2020. [DOI]
A. Parashar, P. Raina, Y. S. Shao, Y. Chen, V. A. Ying, A. Mukkara, R. Venkatesan, B. Khailany, S. W. Keckler, and J. Emer, "Timeloop: A systematic approach to DNN accelerator evaluation," IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS), 2019. [paper]
Y. N. Wu, P.-A. Tsai, A. Parashar, V. Sze, J. S. Emer, "Sparseloop: An Analytical Approach To Sparse Tensor Accelerator Modeling", arXiv, May 2022. [paper]
Y. N. Wu, P.-A. Tsai, A. Parashar, V. Sze, J. S. Emer, “Sparseloop: An Analytical, Energy-Focused Design Space Exploration Methodology for Sparse Tensor Accelerators,” IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS), March 2021 [paper]
Y. N. Wu, J. S. Emer, V. Sze, “Accelergy: An Architecture-Level Energy Estimation Methodology for Accelerator Designs,” International Conference on Computer Aided Design (ICCAD), November 2019 [paper] [slides]
Y.H. Chen, T. Krishna, J. Emer, V. Sze, "Eyeriss: An Energy-Efficient Reconfigurable Accelerator for Deep Convolutional Neural Networks", IEEE Journal of Solid State Circuits (JSSC), ISSCC Special Issue, Vol. 52, No. 1, pp. 127-138, January 2017. [paper]
Y.S. Shao, J. Clemons, R. Venkatesan, B. Zimmer, M. Fojik, N. Jiang, B. Keller, A. Klinefelter, N. Pinckney, P. Raina, S. Tell, Y. Zhang, W.J. Dally, J. Emer, C.T. Gray, B. Khailany, S.W. Kecker, "Simba: Scaling Deep-Learning Inference with Multi-Chip-Module-Based Architecture", 52nd Annual IEEE/ACM International Symposium on Microarchitecture (MICRO), October 2019. [paper]