Overview Previous Versions Timeloop+Accelergy v3 Timeloop Input Formats Design Architecture

Architecture

To describe an architecture in Timeloop, one must specify the hardware organization, i.e., the topology of interconnected compute and storage units using the architecture: top-level key.

The hardware organization is described as a hierarchical tree of storage elements with a set of arithmetic units (such as MACs) at the leaves and a backing store (such as DRAM) holding all of the workload’s data at the root. Timeloop supports an arbitrary number of memory levels. Each level can fan out into an integral multiple of child instances at the next-inner level. For each memory level, the number of instances, entries per instance, bits in each entry, bandwidth, and various other microarchitectural attributes can be specified via YAML.

Note: The basic structure of the architecture: tree is shared with Accelergy, which uses it to characterize the energy and area associated with the components of the architecture. Keys that are not understood by either Timeloop or Accelergy are ignored because they are probably relevant to the other tool.

The `version:` key

Each top-level YAML key used as a Timeloop/Accelergy input has a version. The current version for the archtecture: is 0.2, which is specified as follows:

architecture:
  version: 0.2
  ...

The `subtree:` key

Under the architecture: top-level YAML key, each level of the hierarchy of a design is specified with the subtree: key. The subtree: key has subkeys containing:

name: - A name for the level and an optional specification of the number of instances;
local: - An optional key that describes the hardware local to the level; and/or
subtree: - An optional key that recursively describes lower levels.

Note: At present, a level may have a single subtree at most.

The `name:` key

A single instance of the hardware at level is specified with a simple name in the name: Multiple instances of the hardware at a level is specifed with an array-style designation following the name of the level. For example below is an example where there is a single instance of the top level (GlobalBuffer) and 16 instances of the next level (PE) :

architecture:
   ...

  subtree:
    name: GlobalBuffer
    local:
         ...
    subtree:
        name: PE[0..15]
        ...

The `local:` key

The local: key describes hardware local to the current level of the hardware hierarchy. This key contains a list of records describing each of the hardware components at this level. The keys for each local record are:

name: - A name for the component
class: - The class for the component, which is understood by both Timeloop and Accelergy. From Accelergy's perspective it may be either a primitive or compound component (see TBD)
attributes: - A list of attributes of the component, which is used by Timeloop, e.g., to determine capacity of a storage component, and/or Accelergy, e.g., to determine energy consumption of the component.

For example a level with two local components might look as follows:

architecture:
    ....
    local:
    - name: MainMemory
      class: DRAM
      attributes:
        attr0: ...
        attr1: ...
        ...
    - name: MemoryController
      class: MemoryController
      attributes:
        attr0: ...  
        attr1: ...
        ...

Note: Currently in Timeloop, all non-leaf hardware must only be storage or network components. All compute components must live a the leaves of the tree.

Attributes

The attributes: key of a component contains a list of descriptions of the attributes of a component. These attributes are used by Timeloop and/or Accelergy to accurately model the component.

For example, some important attributes for an SRAM array include its height and width which are used by Timeloop to determine the capacity of the array and by Accelergy to determine the energy per read and write. A typical set of attributes for an SRAM would be as follows:

architecture:
  ...
      - name: Buffer # 256KB buffer
        class: SRAM
        attributes:
          depth: 8192
          width: 256
          block-size: 32
          word-bits: 8
   ...

More details on attributes for different component classes and their attributes can be found here

Full Example

Here is a complete example of an architecture:

architecture:
  version: 0.2
  
  subtree:
  - name: System
    
    local:
    - name: MainMemory
      class: DRAM
      attributes:
        width: 256
        block-size: 32
        word-bits: 8

    subtree:
    - name: Chip
      attributes:
        technology: 40nm

      local:
      - name: GlobalBuffer # 256KB buffer
        class: SRAM
        attributes:
          depth: 8192
          width: 256
          block-size: 32
          word-bits: 8
        
      subtree:
      - name: PE
      
        local:
        - name: RegisterFile
          class: regfile
          attributes:
            depth: 64
            width: 8
            block-size: 1
            word-bits: 8
        - name: MACC
          class: intmac
          attributes:
            datawidth: 8

Architecture

The version: key

The subtree: key

The name: key