Components

In this secion, we only describe the high-level components and the relevant attributes captured by Timeloop. Please also visit the Accelergy Components section to get a more comprehensive view of the different components captured by the Timeloop/Accelergy framework.

Some common component classes and their attributes are:

Storage Classes

storage/SRAM/regfile

The above class names can be used interchangably in architecture specification. This storage class describes a onchip storage with limited amout of space.

Please see below the list of important attributes for the storage class

  • depth (or memory_depth, data_storage_depth): the number of "rows" in the storage
  • width (or memory_width, data_storage_width): number of bits per row
  • block_size (or n-words): number of words per row
  • datawidth (or word-bits, word_width): number of bits per word
  • read_bandwidth: bandwdith provisioned for reads, number of words per cycle
  • write_bandwidth: bandwidth provisioned for fills/updates, number of words per cycle
  • multiple_buffering: specified as a number, e.g., 2 means double buffering
  • n_ports (or num-ports): number of read write ports
  • meshX: spatial x direction total instances
  • meshY: spatial y direction total instances
  • cluster_size: number of copies of the storage unit (only one copy active)
  • metadata_storage_depth: number of rows for metadata storage, useful only if there is representation format specification in sparse optimizations input
  • metadata_storage_width: number of bits per row for metadata storage, useful only if there is representation format specification in sparse optimizations input
  • metadata_word_bits: number of bits per word for metadata storage, useful only if there is representation format specification in sparse optimizations input (note that this value can be overridden by per-rank metadata and payload word-bit specifications in the sparse optimizations input)

DRAM

Describes DRAM storage with unlimited amount of space.

Please see below the list of important attributes for the DRAM class (a subset of storage class attributes).

  • type: DRAM technology, refer to accelergy cacti plug in for the list of supported technologies
  • width (or memory_width, data_storage_width): number of bits per row
  • block_size (or n-words): number of words per row
  • datawidth (or word-bits, word_width): number of bits per word
  • read_bandwidth: bandwdith provisioned for reads
  • write_bandwidth: bandwidth provisioned for fills/updates
  • metadata_storage_width: number of bits per row for metadata storage, useful only if there is representation format specification in sparse optimizations input
  • metadata_word_bits: number of bits per word for metadata storage, useful only if there is representation format specification in sparse optimizations input (note that this value can be overridden by per-rank metadata and payload word-bit specifications in the sparse optimizations input)

Invariants

The specified attributes need to follow the invariants below:

  • datawidth x block_size == width
  • block_size x datawidth x cluster_size == width

Compute classes

compute/mac

The above class names can be used interchangably in architecture specification. This storage class describes a arithmetic unit.

Please see below the list of important attributes for the compute class

  • datawidth (or word-bits): number of bits per word
  • meshX: spatial x direction total instances
  • meshY: spatial y direction total instances

accessibility